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advance data sheet ?2008 cadeka microcircuits llc www.cadeka.com CDK1307 ultra low power, 20/40/65/80msps, 12/13-bit adcs rev 0.1 CDK1307 ultra low power, 20/40/65/80msps, 12/13-bit analog-to-digital converters (adcs) f e a t u r e s n 13-bit resolution n 20/40/65/80msps max sampling rate n ultra-low power dissipation: 19/33/50/60mw n 72.4db snr at 8mhz f in n internal reference circuitry n 1.8v core supply voltage n 1.7 C 3.6v i/o supply voltage n parallel cmos output n 40-pin qfn package n pin compatible with cdk1308 a p p l i c a t i o n s n medical imaging n portable test equipment n digital oscilloscopes n if communication general description the CDK1307 is a high performance ultra low power analog-to-digital converter (adc). the adc employs internal reference circuitry, a cmos control interface and cmos output data, and is based on a proprietary struc - ture. digital error correction is employed to ensure no missing codes in the complete full scale range. two idle modes with fast startup times exist. the entire chip can either be put in standby mode or power down mode. the two modes are optimized to allow the user to select the mode resulting in the smallest possible energy consumption during idle mode and startup. the CDK1307 has a highly linear tha optimized for frequencies up to nyquist. the differential clock interface is optimized for low jitter clock sources and supports lvds, lvpecl, sine wave, and cmos clock inputs. functional block diagram ordering information part number speed package pb-free rohs compliant operating temperature range packaging method CDK1307ailp40 20msps qfn-40 yes yes -40c to +85c tray CDK1307bilp40 40msps qfn-40 yes yes -40c to +85c tray CDK1307cilp40 65msps qfn-40 yes yes -40c to +85c tray CDK1307dilp40 80msps qfn-40 yes yes -40c to +85c tray moisture sensitivity level for all parts is msl-3. a m p l i f y t h e h u m a n e x p e r i e n c e
?2008 cadeka microcircuits llc www.cadeka.com 2 advance data sheet CDK1307 ultra low power, 20/40/65/80msps, 12/13-bit adcs rev 0.1 pin assignments pin no. pin name description 0 vss ground connection for all power domains. exposed pad 1, 11, 16 dvdd digital and i/o-ring pre driver supply voltage, 1.8v 2 cm_ext common mode voltage output 3, 4, 7 avdd analog supply voltage, 1.8v 5, 6 ip, in analog input (non-inverting, inverting) 8 dvddclk clock circuitry supply voltage, 1.8v 9 clkp clock input, non-inverting (format: lvds, lvpecl, cmos/ttl, sine wave) 10 clkn clock input, inverting. for cmos input on clkp, connect clkn to ground 12 clk_ext_en clk_ext signal enabled when low (zero). tristate when high. 13 dfrmt data format selection. 0: offset binary, 1: two's complement 14 pd_n full chip power down mode when low. all digital outputs reset to zero. after chip power up always apply power down mode before using active mode to reset chip. 15 oe_n output enable. tristate when high 17, 18, 25, 26, 36, 37 ovdd i/o ring post-driver supply voltage. voltage range 1.7 to 3.6v 19 d_0 output data (lsb, 13-bit output or 1v pp full scale range) 20 d_1 output data lsb, 12-bit output 2v pp full scale range) 21 d_2 output data 22 d_3 output data pin confguration qfn-40 CDK1307 qfn-40 2 cm_ext 4 avdd 3 avdd 1 dvss 6 in 8 dvddclk 7 avdd 10 clkn 9 clkp 5 ip 29 d_6 27 clk_ext 28 d_5 30 d_7 25 ovdd 23 d_4 24 orng 21 d_2 22 d_3 26 ovdd 12 clk_ext_en 14 pd_n 13 dfrmt 11 dvdd 16 dvdd 18 ovdd 17 ovdd 20 d_1 19 d_0 15 oe_n 39 cm_extbc_0 37 ovdd 38 cm_extbc_1 40 slp_n 35 d_12 33 d_10 34 d_11 31 d_8 32 d_9 36 ovdd
?2008 cadeka microcircuits llc www.cadeka.com 3 advance data sheet CDK1307 ultra low power, 20/40/65/80msps, 12/13-bit adcs rev 0.1 pin no. pin name description 23 d_4 output data 24 orng out of range fag. high when input signal is out of range 27 clk_ext output clock signal for data synchronization. cmos levels 28 d_5 output data 29 d_6 output data 30 d_7 output data 31 d_8 output data 32 d_9 output data 33 d_10 output data 34 d_11 output data (msb for 1v pp full scale range, see reference voltages section) 35 d_12 output data (msb for 2v pp full scale range) 38, 39 cm_extbc_1, cm_extbc_0 bias control bits for the buffer driving pin cm_ext 00: off 10: 50a 10: 500a 11: 1ma 40 slp_n sleep mode when low pin assignments (continued)
?2008 cadeka microcircuits llc www.cadeka.com 4 advance data sheet CDK1307 ultra low power, 20/40/65/80msps, 12/13-bit adcs rev 0.1 absolute maximum ratings the safety of the device is not guaranteed when it is operated above the absolute maximum ratings. the device should not be operated at these absolute limits. adhere to the recommended operating conditions for proper device function. the information contained in the electrical characteristics tables and typical performance plots refect the operating conditions noted on the tables and plots. parameter min max unit avdd -0.3 +2.3 v dvdd -0.3 +2.3 v avss, dvssck, dvss, ovss -0.3 +0.3 v ovdd, ovss -0.3 +3.9 v clkp, clkn -0.3 +3.9 v analog inputs and outpts (ipx, inx) -0.3 +2.3 v digital inputs -0.3 +3.9 v digital outputs -0.3 +3.9 v reliability information parameter min typ max unit junction temperature tbd c storage temperature range -60 +150 c lead temperature (soldering, 10s) tbd c esd protection product qfn-40 human body model (hbm) 2kv charged device model (cdm) tbd recommended operating conditions parameter min typ max unit operating temperature range -40 +85 c
?2008 cadeka microcircuits llc www.cadeka.com 5 advance data sheet CDK1307 ultra low power, 20/40/65/80msps, 12/13-bit adcs rev 0.1 electrical characteristics (avdd = 1.8v, dvdd = 1.8v, dvddclk = 1.8v, ovdd = 2.5v, 20/40/65/80msps clock, 50% clock duty cycle, -1dbfs 8mhz input signal, 13-bit output, unless otherwise noted) symbol parameter conditions min typ max units dc accuracy no missing codes guaranteed offset error midscale offset tbd mv gain error full scale range deviation from typical -6 6 %fs dnl differential non-linearity 12-bit level -0.5 0.5 lsb inl integral non-linearity 12-bit level -1 1 lsb v cmo common mode voltage output v avdd /2 v analog input v cmi input common mode analog input common mode voltage v cm -0.1 v cm +0.1 v v fsr full scale range, normal differential input voltage range, 2.0 v pp full scale range, option differential input voltage range, 1v (see section reference voltages) 1.0 v pp input capacitance differential input capacitance 1.8 pf bandwidth input bandwidth, full power 500 mhz power supply avdd, dvdd core supply voltage supply voltage to all 1.8v domain pins. see pin confguration and description 1.7 1.8 2.0 v ovdd i/o supply voltage output driver supply voltage (ovdd). must be higher than or equal to core supply voltage (v ovdd v ocvdd ) 1.7 2.5 3.6 v
?2008 cadeka microcircuits llc www.cadeka.com 6 advance data sheet CDK1307 ultra low power, 20/40/65/80msps, 12/13-bit adcs rev 0.1 electrical characteristics - CDK1307a (avdd = 1.8v, dvdd = 1.8v, dvddclk = 1.8v, ovdd = 2.5v, 20msps clock, 50% clock duty cycle, -1dbfs 8mhz input signal, 13-bit output, unless otherwise noted) symbol parameter conditions min typ max units performance snr signal to noise ratio f in = 2mhz 72.7 dbfs f in = 8mhz 72.6 dbfs f in ? f s /2 72.3 dbfs f in = 20mhz 72.0 dbfs sinad signal to noise and distortion ratio f in = 2mhz 72.4 dbfs f in = 8mhz 72.0 dbfs f in ? f s /2 71.3 dbfs f in = 20mhz 71.4 dbfs sfdr spurious free dynamic range f in = 2mhz 84.9 dbc f in = 8mhz 88.7 dbc f in ? f s /2 80.1 dbc f in = 20mhz 85.5 dbc hd2 second order harmonic distortion f in = 2mhz -97.6 dbc f in = 8mhz -100 dbc f in ? f s /2 -101 dbc f in = 20mhz -95.7 dbc hd3 third order harmonic distortion f in = 2mhz -94.6 dbc f in = 8mhz -88.7 dbc f in ? f s /2 -80.1 dbc f in = 20mhz -96.8 dbc enob effective number of bits f in = 2mhz 11.7 bits f in = 8mhz 11.7 bits f in ? f s /2 11.6 bits f in = 20mhz 11.6 bits power supply ai dd analog supply current 7.8 ma di dd digital supply current digital core supply 1.0 ma oi dd output driver supply 2.5v output driver supply, sine wave input, f in = 1mhz, clk_ext enabled 1.7 ma 2.5v output driver supply, sine wave input, f in = 1mhz, clk_ext disabled 1.3 ma analog power dissipation 14.0 mw digital power dissipation ovdd = 2.5v, 5pf load on output bits, f in = 1mhz, clk_ext disabled 5.1 mw total power dissipation ovdd = 2.5v, 5pf load on output bits, f in = 1mhz, clk_ext disabled 19.1 mw power down dissipation 9.9 w sleep mode power dissipation, sleep mode 9.2 mw clock inputs max. conversion rate 20 msps min. conversion rate 15 msps
?2008 cadeka microcircuits llc www.cadeka.com 7 advance data sheet CDK1307 ultra low power, 20/40/65/80msps, 12/13-bit adcs rev 0.1 electrical characteristics - CDK1307b (avdd = 1.8v, dvdd = 1.8v, dvddclk = 1.8v, ovdd = 2.5v, 40msps clock, 50% clock duty cycle, -1dbfs 8mhz input signal, 13-bit output, unless otherwise noted) symbol parameter conditions min typ max units performance snr signal to noise ratio f in = 2mhz 73.2 dbfs f in = 8mhz 73.0 dbfs f in ? f s /2 72.5 dbfs f in = 30mhz 71.2 dbfs sinad signal to noise and distortion ratio f in = 2mhz 72.1 dbfs f in = 8mhz 72.0 dbfs f in ? f s /2 71.7 dbfs f in = 30mhz 70.6 dbfs sfdr spurious free dynamic range f in = 2mhz 81.3 dbc f in = 8mhz 82.0 dbc f in ? f s /2 81.6 dbc f in = 30mhz 82.1 dbc hd2 second order harmonic distortion f in = 2mhz -97.5 dbc f in = 8mhz -103 dbc f in ? f s /2 -95.3 dbc f in = 30mhz -85.1 dbc hd3 third order harmonic distortion f in = 2mhz -82.5 dbc f in = 8mhz -85.3 dbc f in ? f s /2 -81.6 dbc f in = 30mhz -95.8 dbc enob effective number of bits f in = 2mhz 11.7 bits f in = 8mhz 11.7 bits f in ? f s /2 11.6 bits f in = 30mhz 11.4 bits power supply ai dd analog supply current 13.4 ma di dd digital supply current digital core supply 1.7 ma oi dd output driver supply 2.5v output driver supply, sine wave input, f in = 1mhz, clk_ext enabled 3.3 ma 2.5v output driver supply, sine wave input, f in = 1mhz, clk_ext disabled 2.4 ma analog power dissipation 24.1 mw digital power dissipation ovdd = 2.5v, 5pf load on output bits, f in = 1mhz, clk_ext disabled 9.1 mw total power dissipation ovdd = 2.5v, 5pf load on output bits, f in = 1mhz, clk_ext disabled 33.2 mw power down dissipation 9.7 w sleep mode power dissipation, sleep mode 14.2 mw clock inputs max. conversion rate 40 msps min. conversion rate 20 msps
?2008 cadeka microcircuits llc www.cadeka.com 8 advance data sheet CDK1307 ultra low power, 20/40/65/80msps, 12/13-bit adcs rev 0.1 electrical characteristics - CDK1307c (avdd = 1.8v, dvdd = 1.8v, dvddclk = 1.8v, ovdd = 2.5v, 65msps clock, 50% clock duty cycle, -1dbfs 8mhz input signal, 13-bit output, unless otherwise noted) symbol parameter conditions min typ max units performance snr signal to noise ratio f in = 8mhz 73.1 dbfs f in = 20mhz 72.2 dbfs f in ? f s /2 71.6 dbfs f in = 40mhz 70.4 dbfs sinad signal to noise and distortion ratio f in = 8mhz 72.0 dbfs f in = 20mhz 71.8 dbfs f in ? f s /2 70.7 dbfs f in = 40mhz 69.6 dbfs sfdr spurious free dynamic range f in = 8mhz 82.1 dbc f in = 20mhz 84.8 dbc f in ? f s /2 78.7 dbc f in = 40mhz 79.6 dbc hd2 second order harmonic distortion f in = 8mhz -97.3 dbc f in = 20mhz -101 dbc f in ? f s /2 -90.4 dbc f in = 40mhz -91.1 dbc hd3 third order harmonic distortion f in = 8mhz -84.2 dbc f in = 20mhz -90.2 dbc f in ? f s /2 -78.7 dbc f in = 40mhz -89.7 dbc enob effective number of bits f in = 8mhz 11.7 bits f in = 20mhz 11.6 bits f in ? f s /2 11.5 bits f in = 40mhz 11.3 bits power supply ai dd analog supply current 20.4 ma di dd digital supply current digital core supply 2.3 ma oi dd output driver supply 2.5v output driver supply, sine wave input, f in = 1mhz, clk_ext enabled 5.1 ma 2.5v output driver supply, sine wave input, f in = 1mhz, clk_ext disabled 3.5 ma analog power dissipation 36.7 mw digital power dissipation ovdd = 2.5v, 5pf load on output bits, f in = 1mhz, clk_ext disabled 12.9 mw total power dissipation ovdd = 2.5v, 5pf load on output bits, f in = 1mhz, clk_ext disabled 49.6 mw power down dissipation 9.3 w sleep mode power dissipation, sleep mode 20.4 mw clock inputs max. conversion rate 65 msps min. conversion rate 40 msps
?2008 cadeka microcircuits llc www.cadeka.com 9 advance data sheet CDK1307 ultra low power, 20/40/65/80msps, 12/13-bit adcs rev 0.1 electrical characteristics - CDK1307d (avdd = 1.8v, dvdd = 1.8v, dvddclk = 1.8v, ovdd = 2.5v, 80msps clock, 50% clock duty cycle, -1dbfs 8mhz input signal, 13-bit output, unless otherwise noted) symbol parameter conditions min typ max units performance snr signal to noise ratio f in = 8mhz 72.4 dbfs f in = 20mhz 71.8 dbfs f in = 30mhz 71.0 dbfs f in ? f s /2 70.5 dbfs sinad signal to noise and distortion ratio f in = 8mhz 70.7 dbfs f in = 20mhz 70.8 dbfs f in = 30mhz 70.2 dbfs f in ? f s /2 69.6 dbfs sfdr spurious free dynamic range f in = 8mhz 78.2 dbc f in = 20mhz 79.4 dbc f in = 30mhz 79.1 dbc f in ? f s /2 79.7 dbc hd2 second order harmonic distortion f in = 8mhz -97.2 dbc f in = 20mhz -94.2 dbc f in = 30mhz -91.6 dbc f in ? f s /2 -81.8 dbc hd3 third order harmonic distortion f in = 8mhz -78.2 dbc f in = 20mhz -79.4 dbc f in = 30mhz -83.0 dbc f in ? f s /2 -79.7 dbc enob effective number of bits f in = 8mhz 11.5 bits f in = 20mhz 11.5 bits f in = 30mhz 11.4 bits f in ? f s /2 11.3 bits power supply ai dd analog supply current 24.5 ma di dd digital supply current digital core supply 2.9 ma oi dd output driver supply 2.5v output driver supply, sine wave input, f in = 1mhz, clk_ext enabled 6.1 ma 2.5v output driver supply, sine wave input, f in = 1mhz, clk_ext disabled 4.1 ma analog power dissipation 44.1 mw digital power dissipation ovdd = 2.5v, 5pf load on output bits, f in = 1mhz, clk_ext disabled 15.5 mw total power dissipation ovdd = 2.5v, 5pf load on output bits, f in = 1mhz, clk_ext disabled 59.6 mw power down dissipation 9.1 w sleep mode power dissipation, sleep mode 24.1 mw clock inputs max. conversion rate 80 msps min. conversion rate 65 msps
?2008 cadeka microcircuits llc www.cadeka.com 10 advance data sheet CDK1307 ultra low power, 20/40/65/80msps, 12/13-bit adcs rev 0.1 digital and timing electrical characteristics (avdd = 1.8v, dvdd = 1.8v, dvddclk = 1.8v, ovdd = 2.5v, 20/40/65/80msps clock, 50% clock duty cycle, -1 dbfs input signal, 5pf capacitive load, unless otherwise noted) symbol parameter conditions min typ max units clock inputs duty cycle 20 80 % high compliance cmos, lvds, lvpecl, sine wave input range differential input swing -200 200 mv pp differential input swing, sine wave clock input -800 800 mv pp input common mode voltage keep voltages within ground and voltage of ov dd 0.3 v ovdd -0.3 v input capacitance differential 1.7 pf timing t pd start up time from power down from power down mode to active mode references has reached 99% of fnal value 900 clk cycles t slp start up time from sleep from sleep mode to active mode 0.5 s t ovr out of range recovery time 1 clk cycles t ap aperture delay 0.8 ns rms aperture jitter <0.5 ps t lat pipeline delay 12 clk cycles t d output delay 5pf load on output bits (see timing diagram) 4 ns 10pf load on output bits (see timing diagram) tbd ns t dc output delay relative to clk_ext see timing diagram 2 ns logic inputs v ih high level input voltage v ovdd 3.0v 2 v v ovdd = 1.7v C 3.0v 0.8 ? v ovdd v v il low level input voltage v ovdd 3.0v 0 0.8 v v ovdd = 1.7v C 3.0v 0 0.2 ? v ovdd v i ih high level input leakage current -10 10 a i il low level input leakage current -10 10 a c i input capacitance 3 pf logic outputs v oh high level output voltage -0.1 + v ovdd v v ol low level output voltage 0.1 v c l max capacitive load post-driver supply voltage equal to pre-driver supply voltage v ovdd = v ocvdd 5 pf post-driver supply voltage above 2.25v (1) 10 pf note: (1) the outputs will be functional with higher loads. however, it is recommended to keep the load on output data bits as low as possible to keep dynamic currents and resulting switching noise at a minimum.
?2008 cadeka microcircuits llc www.cadeka.com 11 advance data sheet CDK1307 ultra low power, 20/40/65/80msps, 12/13-bit adcs rev 0.1 recommended usage analog input the analog inputs to the CDK1307 is a switched capacitor track-and-hold amplifer optimized for differential opera - tion. operation at common mode voltages at mid supply is recommended even if performance will be good for the ranges specifed. the cm_ext pin provides a voltage suit - able as common mode voltage reference. the internal buffer for the cm_ext voltage can be switched off, and driving capabilities can be changed by using the cm_ext - bc control input. figure 2 shows a simplifed drawing of the input net - work. the signal source must have suffciently low output impedance to charge the sampling capacitors within one clock cycle. a small external resistor (e.g. 22) in series with each input is recommended as it helps reducing transient currents and dampens ringing behavior. a small differential shunt capacitor at the chip side of the resistors may be used to provide dynamic charging currents and may improve performance. the resistors form a low pass flter with the capacitor, and values must therefore be determined by requirements for the application. figure 2. input confguration dc-coupling figure 3 shows a recommended confguration for dc- coupling. note that the common mode input voltage must be controlled according to specifed values. preferably, the cm_ext output should be used as a reference to set the common mode voltage. the input amplifer could be inside a companion chip or it could be a dedicated amplifer. several suitable single ended to differential driver amplifers exist in the market. the system designer should make sure the specifcations of the selected amplifer is adequate for the total system, and that driving capabilities comply with the CDK1307 in - put specifcations. figure 3. dc-coupled input detailed confguration and usage instructions must be found in the documentation of the selected driver, and the values given in figure 3 must be varied according to the recommendations for the driver. ac-coupling a signal transformer or series capacitors can be used to make an ac-coupled input network. figure 4 shows clk_ext n-13 n+1 n+2 n+3 n+4 n+5 n figure 1. timing diagram pf
?2008 cadeka microcircuits llc www.cadeka.com 12 advance data sheet CDK1307 ultra low power, 20/40/65/80msps, 12/13-bit adcs rev 0.1 a recommended confguration using a transformer. make sure that a transformer with suffcient linearity is selected, and that the bandwidth of the transformer is appropriate. the bandwidth should exceed the sampling rate of the adc with at least a factor of 10. it is also important to keep phase mismatch between the differential adc inputs small for good hd2 performance. this type of transformer coupled input is the preferred confguration for high fre - quency signals as most differential amplifers do not have adequate performance at high frequencies. if the input signal is traveling a long physical distance from the signal source to the transformer (for example a long cable), kick- backs from the adc will also travel along this distance. if these kick-backs are not terminated properly at the source side, they are refected and will add to the input signal at the adc input. this could reduce the adc performance. to avoid this effect, the source must effectively terminate the adc kick-backs, or the traveling distance should be very short. if this problem could not be avoided, the cir - cuit in figure 6 can be used. figure 4. transformer-coupled input figure 5 shows ac-coupling using capacitors. resistors from the cm_ext output, r cm , should be used to bias the differential input signals to the correct voltage. the series capacitor, c i , form the high-pass pole with these resistors, and the values must therefore be determined based on the requirement to the high-pass cut-off frequency. figure 5. ac-coupled input note that startup time from sleep mode and power down mode will be affected by this flter as the time required to charge the series capacitors is dependent on the flter cut-off frequency. if the input signal has a long traveling distance, and the kick-backs from the adc not are effectively terminated at the signal source, the input network of figure 6 can be used. the confguration is designed to attenuate the kickback from the adc and to provide an input impedance that looks as resistive as possible for frequencies below nyquist. values of the series inductor will however depend on board design and conversion rate. in some instances a shunt ca - pacitor in parallel with the termination resistor (e.g. 33pf) may improve adc performance further. this capacitor at - tenuate the adc kick-back even more, and minimize the kicks traveling towards the source. however, the imped - ance match seen into the transformer becomes worse. figure 6. alternative input network clock input and jitter considerations typically high-speed adcs use both clock edges to gener - ate internal timing signals. in the CDK1307 only the rising edge of the clock is used. hence, input clock duty cycles between 20% and 80% is acceptable. the input clock can be supplied in a variety of formats. the clock pins are ac-coupled internally, and hence a wide common mode voltage range is accepted. differential clock sources as lvds, lvpecl or differential sine wave can be connected directly to the input pins. for cmos inputs, the clkn pin should be connected to ground, and the cmos clock signal should be connected to clkp. for differential sine wave clock input the amplitude must be at least 800mv pp . 33 33 r t 47 pf pf 120nh 120nh 33 33 r t 68 220 optional 1:1
?2008 cadeka microcircuits llc www.cadeka.com 13 advance data sheet CDK1307 ultra low power, 20/40/65/80msps, 12/13-bit adcs rev 0.1 the quality of the input clock is extremely important for high-speed, high-resolution adcs. the contribution to snr from clock jitter with a full scale signal at a given frequency is shown in the equation below: snr jitter = 20 ? log (2 ? ? f in ? t ) where f in is the signal frequency, and t is the total rms jitter measured in seconds. the rms jitter is the total of all jitter sources including the clock generation circuitry, clock distribution and internal adc circuitry. for applications where jitter may limit the obtainable per - formance, it is of utmost importance to limit the clock jitter. this can be obtained by using precise and stable clock references (e.g. crystal oscillators with good jitter specifcations) and make sure the clock distribution is well controlled. it might be advantageous to use analog power and ground planes to ensure low noise on the supplies to all circuitry in the clock distribution. it is of utmost im - portance to avoid crosstalk between the adc output bits and the clock and between the analog input signal and the clock since such crosstalk often results in harmonic distortion. the jitter performance is improved with reduced rise and fall times of the input clock. hence, optimum jitter per - formance is obtained with lvds or lvpecl clock with fast edges. cmos and sine wave clock inputs will result in slightly degraded jitter performance. if the clock is generated by other circuitry, it should be re- timed with a low jitter master clock as the last operation before it is applied to the adc clock input. digital outputs digital output data are presented on parallel cmos form. the voltage on the ovdd pin set the levels of the cmos outputs. the output drivers are dimensioned to drive a wide range of loads for ovdd above 2.25v, but it is rec - ommended to minimize the load to ensure as low transient switching currents and resulting noise as possible. in ap - plications with a large fanout or large capacitive loads, it is recommended to add external buffers located close to the adc chip. the timing is described in the timing diagram section. note that the load or equivalent delay on ck_ext always should be lower than the load on data outputs to ensure suffcient timing margins. the digital outputs can be set in tristate mode by setting the oe_n signal high. the CDK1307 employs digital offset correction. this means that the output code will be 4096 with shorted inputs. however, small mismatches in parasitics at the input can cause this to alter slightly. the offset correction also re - sults in possible loss of codes at the edges of the full scale range. with no offset correction, the adc would clip in one end before the other, in practice resulting in code loss at the opposite end. with the output being centered digitally, the output will clip, and the out of range fags will be set, before max code is reached. when out of range fags are set, the code is forced to all ones for over-range and all zeros for under-range. data format selection the output data are presented on offset binary form when dfrmt is low (connect to ov ss ). setting dfrmt high (connect to ov dd ) results in 2s complement output format. details are shown in table 1 on page 14. the data outputs can be used in three different confgurations. normal mode: all 13-bits are used. msb is d_12 and lsb is d_0. this mode gives optimum performance due to reduced quanti - zation noise. 12-bit mode: the lsb is left unconnected such that only 12 bits are used. msb is d_12 and lsb is d_1. this mode gives slightly reduced performance, due to increased quantization noise. reduced full scale range mode: the full scale range is reduced from 2v pp to 1v pp which is equivalent to 6db gain in the adc frontend. msb is d_11 and lsb is d_0. note that the codes will wrap around when exceeding the full scale range, and that out of range bits should be used to clamp output data. see section reference voltages for details. this mode gives slightly reduced performance.
?2008 cadeka microcircuits llc www.cadeka.com 14 advance data sheet CDK1307 ultra low power, 20/40/65/80msps, 12/13-bit adcs rev 0.1 table 2: data format description for 1v pp full scale range differential input voltage (ip - in) output data: d_11: d_0 (dfrmt = 0) (2s complement) out of range (use logical and function for &) output data: d_11: d_0 (dfrmt = 1) (2s complement) out of range (use logical and function for &) > 0.5v 0111 1111 1111 d_12 = 1 & d_11 = 1 0111 1111 1111 d_12 = 0 & d_11 = 1 0.5v 0111 1111 1111 0111 1111 1111 +0.24mv 0000 0000 0000 0000 0000 0000 -0.24mv 1111 1111 1111 1111 1111 1111 -0.5v 1000 0000 0000 1000 0000 0000 < -0.5v 1000 0000 0000 d_12 = 0 & d_11 = 0 1000 0000 0000 d_12 = 1 & d_11 = 0 reference voltages the reference voltages are internally generated and buff - ered based on a bandgap voltage reference. no external decoupling is necessary, and the reference voltages are not available externally. this simplifes usage of the adc since two extremely sensitive pins, otherwise needed, are removed from the interface. if a lower full scale range is required the 13-bit output word provides suffcient resolution to perform digital scaling with an equivalent impact on noise compared to adjusting the reference voltages. a simple way to obtain 1.0v pp input range with a 12-bit output word is shown in the table 2 below. note that only 2s complement output data are available in this mode and that out of range conditions must be determined based on a two bit output. the output code will wrap around when the code goes outside the full scale range. the out of range bits should be used to clamp the output data for overrange conditions. operational modes the operational modes are controlled with the pd_n and slp_n pins. if pd_n is set low, all other control pins are overridden and the chip is set in power down mode. in this mode all circuitry is completely turned off and the internal clock is disabled. hence, only leakage current contributes to the power down dissipation. the startup time from this mode is longer than for other idle modes as all references need to settle to their fnal values before normal operation can resume. the slp_n bus can be used to power down each channel independently, or to set the full chip in sleep mode. in this mode internal clocking is disabled, but some low band - width circuitry is kept on to allow for a short startup time. however, sleep mode represents a signifcant reduction in supply current, and it can be used to save power even for short idle periods. the input clock could be kept running in all idle modes. however, even lower power dissipation is possible in power down mode if the input clock is stopped. in this case it is important to start the input clock prior to en - abling active mode. table 1: data format description for 2v pp full scale range differential input voltage (ip - in) output data: d_12 : d_0 (dfrmt = 0, offset binary) output data: d_12 : d_0 (dfrmt = 1, 2s complement) 1.0 v 1 1111 1111 1111 0 1111 1111 1111 +0.24mv 1 0000 0000 0000 0 0000 0000 0000 -0.24mv 0 1111 1111 1111 1 1111 1111 1111 -1.0v 0 0000 0000 0000 1 0000 0000 0000
for additional information regarding our products, please visit cadeka at: cadeka.com cadeka, the cadeka logo design, comlinear and the comlinear logo design are trademarks or registered trademarks of cadeka microcircuits llc. all other brand and product names may be trademarks of their respective companies. cadeka reserves the right to make changes to any products and services herein at any time without notice. cadeka does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by cadeka; nor does the purchase, lease, or use of a product or service from cadeka convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of cadeka or of third parties. copyright ?2008 by cadeka microcircuits llc. all rights reserved. cadeka headquarters loveland, colorado t: 970.663.5452 t: 877.663.5452 (toll free) advance data sheet designed by CDK1307 ultra low power, 20/40/65/80msps, 12/13-bit adcs rev 0.1 mechanical dimensions qfn-40 package note: package dimensions in millimeter unless otherwise noted. symbol min typ max min typ max a ? ? 0.035 ? ? 0.9 a 1 0.001 0.0004 0.002 0.00 0.01 0.05 a 2 ? 0.023 0.028 ? 0.65 0.7 a 3 0.008 ref 0.2 ref b 0.008 0.010 0.013 0.2 0.25 0.32 d 0.236 bsc 6.00 bsc d 1 0.226 bsc 5.75 bsc d 2 0.156 0.162 0.167 3.95 4.10 4.25 l 0.012 0.016 0.020 0.3 0.4 0.5 e 0.020 bsc 0.50 bsc 1 0 ? 12 0 ? 12 f 0.008 ? ? 0.2 ? ? g 0.0096 0.0168 0.024 0.24 0.42 0.6 r 0.004 0.008 ? 0.1 0.2 ? inches millimeters pin 1 id - dia. 0.5 (top side) pin 1 id - dia. r pin 0 exposed pad f g a a3 a1 a2 1 l b e 1.14 0.45 d d2 d d2 d1 a m p l i f y t h e h u m a n e x p e r i e n c e

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